Recent s.s.t.c work

["Tesla list" <tesla@xxxxxxxxxx>]

Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

Steve & List-

List:  Having seen Steve Ward's postings on his super s.s.t.c., I've had my 
motivation revived & have been developing a re-working of mine of a few 
years back--which was not-so-super.  But it did work & I did make a nice 
photo of it running!

Steve:  I respond to your latest off-List email here.

I'll ask Terry to post my drive-IGBT4.jpg schematic and also a picture of 
my primary assy on hot-streamer.  Presumably

http://hot-streamer.com/temp/drive-IGBT4.jpg

 and

http://hot-streamer.com/temp/KCH_pri3.jpg

I invite comments from the List--& from Steve, of course.

The schematic is a drawing from simulation; that's as far as I've gotten so 
far in building the electronics.  V2 simulates a UCC37321/-2 IC-pair with 
each one coupling to the transformer thru a pair of NPN/PNP "totem-pole" 
emitter followers.  R8 simulates some internal resistance.

In hardware, TX1 will be wound 1:2:2:2:2 on a toroidal ferrite core (~3" in 
diameter).  The circuit shown will drive an IGBT in a pair of Siemens BSM 
150 GB 100 D "bricks", in an H-bridge configuration; there will be 4 such 
circuits--except that only one cut-off portion (far right) will be 
included, to control the 2 "lower" drive circuits of the H-bridge.

Storage capacitors C2 & C5 are charged thru TX1, C4 and the forward-biased 
base:collector junctions of Q1 & Q3.  The TX1 signal is there all the time 
since I will utilize a "startup" oscillator to get primary-feedback 
oscillation going for each spark event.  With no spark, a gate signal from 
V3 drives the LEDs in all 4 of the U1 opto-isolators, keeping the Q2s 
off.  Thus the only signals reaching the IGBT gates are negative levels 
coupled through the D1s.  The incorporation of the C4s allows for unequal 
voltage levels to be reached on C2 and C5: -15V on C5 but 25V on C2--and 
keeps dc out of the transformer.  The schematic shows 2 zeners across C2 
due to a limitation of the simulator.

When a spark is to be generated, the U1s turn off, the Q2s turn on (from 
current thru the R1s) and +25V pulse-levels are coupled to the IGBT 
gates.  The "upper" two drive circuits float, of course, being referenced 
to the respective sources of the "upper" IGBTs.  The + and - levels to the 
IGBTs are provided from the Q1/Q3 emitter-follower pairs; since the C2s & 
C5s are already charged up via the b:c junctions, the transistors operate 
properly--until, of course, each one might run out of collector voltage at 
the extreme of its base-voltage excursion, but by then...no problem: the 
IGBTs are on or off.

Crossover-conduction in the IGBTs is precluded due to the on-resistances of 
the Q2s: they are momentarily pulled out of saturation during each positive 
excursion of the drive, nicely providing the requisite turn-on 
delays.  Simulation shows signal cross-over at -10 V.

I'll hope that the overload-cutoff circuit I've included will save a brick 
should a component (or design!) failure initiate upper:lower conduction in 
the H-bridge--or, should the IGBTs start to carry too much signal 
current.  I'll connect a single R11 in series with the negative-supply 
electrolytics that provide power to the bridge; I'm going to 
half-wave-rectify off the mains to charge up a pair of positive-supply and 
negative-supply electrolytics--to yield ~ twice the mains peak across the 
bridge.

The cutoff circuit of Q6 & Q5 is triggered by >~1 V across R11.  It 
operates to dump the charge of the two "lower" C2s, doing that, in 
simulation, to +5 V within 220 us.  Perhaps someone has an opinion as to 
whether that's fast enough to save a brick in the event of full upper:lower 
conduction.

The photo shows my primary: 6 turns of paralleled 1/4" Cu tubing wound 
inside an 18-gallon plastic bucket.  The main part of an identical 
bucket--but polypropylene and not butyrate--is cemented inside the lower 
end of the secondary, so that when the secondary is placed over the 
primary, voltage-withstanding is improved by the interposition of two 
bucket-thicknesses, with no holes in them since I use nylon screws to 
secure the coil-holders.  I hope...I hope that that will be enough!

I've located the MMC array so as to constitute, in effect, another turn on 
the primary.  As noted on the photo, the lower rim of the secondary will 
sit somewhat above the level of the capacitors, so that that capacitor-turn 
will couple a bit inefficiently, but no matter.  The MMC array and coil are 
in series, of course, and are to be connected (via copper braid) to the 
output nodes of the H-bridge.  I will position the bridge-proper, the 
power-capacitors, and all the electronics--except for a small duty-cycle 
oscillator which might be susceptible to EMI--directly below the primary 
assembly (& a bit off to one side), for short lead-lengths between primary 
and bridge.

So it comes along.  But at my age I'm a bit running out of time so I must 
keep at it!

Ken Herrick